Job Title: Technologist, 3D Integration and Advanced Packaging

Job Code: 17329

Job Location: Palm Bay, FL

Job Schedule: 9/80 (Every other Friday off!)

Relocation: Relocation assistance is available for qualified candidates

Job Description:

This is an exciting senior level role responsible for leading 3D semiconductor packaging solutions and heterogeneous integration solutions. Work across the industry to identify partners, tools, and technologies to develop advanced packaging solutions for 3D-ICs, 2.5D, chiplets, silicon interposers, and other applications utilizing high density interconnect such as wafer-to-wafer and die-to-wafer stacking. This key role will provide technical insight for our existing technologies and develop new technologies to capture and lead new programs with our military, government, and commercial customers.   

Essential Functions: 

• Technical and business leadership focused on developing 3D packaging solutions such as fine pitch electrical interconnects, die-to-wafer, and wafer-to-wafer stacking
• Establish strategic direction for new processes and integration strategies for design, process, metrology, and IP technology transfers
• Lead intra and inter technology transfer for advanced packaging including process documentation (i.e. PDKs, tool lists, process or record, etc.) process engineering (i.e. transfer tutorials, training, engineering support, reliability, etc.) and process calibration (test chip design, calibration wafers, etc.)
• Represent the organization as the prime technical contact on contracts and projects. Interacts with senior external personnel on significant technical matters often requiring coordination between organizations.
• Own and develop tactical and operational strategies that enable advanced packaging business to scale
• Develop collaborative relationships with Engineering Managers and Program Leadership to support business demands including bid and proposal
• Domestic and International Travel Required up to 25% of time

Qualifications:

• Bachelor’s Degree and a minimum of 15 years of prior relevant experience or Graduate Degree and a minimum of 13 years of prior related experience. In lieu of a degree, minimum of 19 years of prior related experience.
• Ability to obtain a US government Security Clearance at the TS/SCI level
• 9+ years experience in wafer level packagin from R&D to Development and into Production
• Prior or current experience with management skills, including demonstrated ability to think end-to-end and manage multiple priorities / projects simultaneously
• Experience in engineering leadership and business development
• Experience in BEOL (Back End of Line) processes including ASML i-line photolithography, microbumping, TSV plating, CMP, etc.

Preferred Additional Skills:

• Experience with IP licensing and technology transfer